Hi!

I'm Andrew,

an electrical engineering student excited about building hardware.

Andrew Lu
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About

My name is Andrew, and I am a sophomore at Purdue University studying electrical engineering. I grew up always trying to understand how things really worked, yet all sorts of mysteries surrounding computers, cars, phones, Wi-Fi, satellites, and more remained as I grew older. This curiosity and the amount of ingenuity and innovation that is happening in these fields has pushed me to dive into electrical engineering. Nowadays, you'll often find me digging into computer architecture, chip design, embedded systems, semiconductor advancements, and the math & physics behind it all.


I am currently expanding a single cycle RISC-V CPU to include staged pipelining and peripherals in Vivado, as well as simulating a custom built 6-axis robotic arm in ROS. With the insights I've gained and will learn about in my projects and experiences, I hope to build the next generation of hardware that propels society forward, from renewable energy to advancing chip design and beyond.

Experience

Company Logo

Undergraduate Researcher, Digital Design

Purdue System-on-Chip Extension Technologies | August 2025 - Present
  • Working in team projects focusing on industry chip design
  • Designed and verified a USB Transceiver following USB 2.0 Protocols in SystemVerilog
  • Built Atari's Asteroids game in SystemVerilog, undergoing the full ASIC Design Flow, with the GDSII file sent for tapeout in May 2026 on ChipFoundry
  • SystemVerilog, ASIC Design Flow (RTL Design, RTL Verification, GTKWave, Yosys, OpenLane, GDSII)

Projects

6-Axis Robotic Arm

6-Axis Robotic Arm (In Progress)

Custom hardware combining KiCad PCB design, C++ on a Raspberry Pi Pico, and ROS2 architecture.

RISC-V CPU

Single-Cycle RISC-V CPU

Built datapath and control modules for a single-cycle RISC-V CPU simulated on an UPduino v3.1 FPGA. Single-cycle implementation is currently being expanded to include pipelining.

Asteroids Game

Hardware Asteroids Game

A hardware recreation of Atari's Asteroids covering the ASIC design flow from RTL design to GDSII file creation, with the design sent for tapeout on ChipFoundry.

USB Transceiver

USB 2.0 Transceiver

Designed, built, and simulated a transceiver in SystemVerilog featuring NRZI encoding and bit stuffing.

Skills

SystemVerilog
C / C++
Python
Altium Designer
KiCad
FPGAs
ASIC Design
ROS2
Microcontrollers
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